Mark Heinrich

 

Associate Professor, CS

School of Electrical Engineering and Computer Science

 

Mailing Address: 

Computer Science Dept, University of Central Florida

4000 Central Florida Blvd.

Orlando, FL 32816-2362

 

Email: heinrich@cs.ucf.edu

Office: CSB 252

Phone: (407) 823-5341

Fax: (407) 823-5419

Research Interests

Computer architecture, parallel computer architecture, active memory and I/O systems, scalable cache coherence protocols, system-area networks, multiprocessor simulation methodology, and hardware/software co-design.

Bio

Started at UCF as an Associate Professor in January, 2003.  Prior to that, I was an Assistant Professor in the School of Electrical and Computer Engineering at Cornell University, a co-founder of its Computer Systems Laboratory, and a member of the Intelligent Information Systems Institute.  I received my Ph.D. in Electrical Engineering from Stanford University under John Hennessy in 1998 where I was a principal designer of the FLASH multiprocessor; the author of FlashLite, the system-level simulator of the FLASH machine; and the designer of four cache coherence protocols for FLASH (bitvector/coarsevector, dynamic pointer allocation, SCI, and a 2-bit protocol). I received my MS from Stanford in 1993, and my BSE in Electrical Engineering and Computer Science from Duke University in 1991. I was also the co-founder and Chief Architect of Flashbase, Inc. an Internet company specializing in automated sweepstakes and database-backed forms and tools for customer acquisition.

Oh, I am a HUGE sports fan. When I'm not browsing ESPN's Sportszone, I'm usually checking out Duke sports news at  Duke Basketball Report.

Teaching

Fall 2003: CDA 4150  Computer Architecture

Publications

M. Chaudhuri, M. Heinrich, C. Holt, et al. "Latency, Occupancy, and Bandwidth in DSM Multiprocessors: A Performance Evaluation". To appear in IEEE Transactions on Computers, 52(7), July 2003. (PDF)

M. Heinrich and M. Chaudhuri. "Ocean Warning: Avoid Drowning".   (To appear in Computer Architecture News), June 2003. 

D. Kim, M. Chaudhuri, and M. Heinrich. "Active Memory Techniques for ccNUMA Multiprocessors".   In Proceedings of the 17th International Parallel and Distributed Processing Symposium (IPDPS)), April 2003. (PDF)

M.Chaudhuri and M. Heinrich.  "Exploring Virtual Network Selection Algorithms in DSM Cache Coherence Protocols". (Submitted to IEEE Transactions on Parallel and Distributed Systems (TPDS)), March 2003.

M. Hao and M. Heinrich. "Active I/O Switches in System Area Networks".   In Proceedings of the 9th International Symposium on High-Performance Computer Architecture (HPCA), pages 365-376, February 2003. (PDF)

M. Chaudhuri, and M. Heinrich. "The Impact of Negative Acknowledgments in Shared Memory Scientific Applications".   (Submitted to IEEE Transactions on Parallel and Distributed Systems (TPDS)), January 2003. 

D. Kim, M.Chaudhuri, M. Heinrich, and E. Speight.  "Architectural Support for Uniprocessor and Multiprocessor Active Memory Systems". (To appear in IEEE Transactions on Computers), November 2002.

D. Kim, M. Chaudhuri, and M. Heinrich. "Leveraging Cache Coherence in Active Memory Systems".   In Proceedings of the 16th International Conference on Supercomputing (ICS), pages 2-13, June 2002.  (PDF)

M. Chaudhuri, D. Kim, and M. Heinrich. "Cache Coherence Protocol Design for Active Memory Systems". In Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications (PDPTA), pages 83-89, June 2002.  (PDF)

M. Heinrich, E. Speight, and M. Chaudhuri. "Active Memory Clusters: Efficient Multiprocessing on Commodity Clusters". In Proceedings of the Fourth International Symposium on High-Performance Computing (ISHPC), Lecture Notes in Computer Science, vol. 2327, Springer-Verlag, pages 78-92, May 2002.  (PDF)

M. Heinrich and E. Speight. "Providing Hardware DSM Performance at Software DSM Cost". Cornell Computer Systems Lab Technical Report CSL-TR-2000-1008, November 2000. (Postscript)

J. Gibson, R. Kunz, D. Ofelt, M. Horowitz, J. Hennessy, and M. Heinrich. "FLASH vs. (Simulated) FLASH: Closing the Simulation Loop". In Proceedings of the 9th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), pages 49-58, November 2000. (PDF)

A. Chou, B. Chelf, D. Engler, and M. Heinrich. "Using Meta-Level Compilation to Check FLASH Protocol Code". In Proceedings of the 9th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), pages 59-70, November 2000. (Postscript)

R. Manohar and M. Heinrich. "A Case For Asynchronous Active Memories". ISCA 2000 Solving the Memory Wall Problem Workshop, June 2000.  (Postscript)

R. Manohar and M. Heinrich. "The Branch Processor Architecture". Cornell Computer Systems Lab Technical Report CSL-TR-1999-1000, November 1999. (Postscript)

J. Hennessy, A. Gupta, and M. Heinrich, "Cache-Coherent Distributed Shared Memory: Perspectives on Its Development and Future Challenges". Proceedings of the IEEE, 87(3):418-429, Special Issue on Distributed Shared Memory, March 1999. (Postscript)

M. Heinrich, R. Soundararajan, J. Hennessy, and A. Gupta, "A Quantitatitve Analysis of the Performance and Scalability of Distributed Shared Memory Cache Coherence Protocols". IEEE Transactions on Computers, 48(2):205-217, Special Issue on Cache Memory and Related Problems, February 1999. (PDF)

M. Heinrich, "The Performance and Scalability of Distributed Shared Memory Cache Coherence Protocols". Ph.D. Dissertation, Stanford University, October 1998.

R. Soundararajan, M. Heinrich, B. Verghese, et al. "Flexible Use of Memory for Replication/Migration in Cache-Coherent DSM Multiprocessors". In Proceedings of the 25th International Symposium on Computer Architecture (ISCA), pages 342-355, June 1998.  (Postscript)

K. Olukotun, M. Heinrich, and D. Ofelt, "Digital System Simulation: Methodologies and Examples". In Proceedings of the 35th Design Automation Conference (DAC), pages 658-663, June 1998. (Postscript)

M. Heinrich, D. Ofelt, M. Horowitz, and J. Hennessy, "Hardware/Software Codesign of the Stanford FLASH Multiprocessor". In Proceedings of the IEEE Special Issue on Hardware/Software Co-design, Vol. 85, No. 3, March 1997.  (Postscript)

M. Martonosi, D. Ofelt, and M. Heinrich, "Integrating Performance Monitoring and Communication in Parallel Computers". In ACM SIGMETRICS International Conference on Measurement and Modeling of Computer Systems, pp. 138-147, May 1996.  (Postscript)

J. Hennessy and M. Heinrich, "Hardware/Software Co-Design of Processors: Concepts and Examples". In Hardware/Software Co-design, edited by G. de Micheli and M. Sami, Dordecht; Boston: Kluwer Academic Publishers, c. 1996.  (Postscript)

C. Holt, M. Heinrich, J.P. Singh, et al., "The Effects of Latency, Occupancy, and Bandwidth in Distributed Shared Memory Multiprocessors". Stanford University Technical Report CSL-TR-95-660, January 1995.  (Postscript)

M. Heinrich, J. Kuskin, D. Ofelt, et al., "The Performance Impact of Flexibility in the Stanford FLASH Multiprocessor". In Proceedings of the 6th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), pages 274-285, 1994.  (Postscript)

J. Kuskin, D. Ofelt, M. Heinrich, et al., "The Stanford FLASH Multiprocessor". In Proceedings of the 21st International Symposium on Computer Architecture (ISCA), pages 302-313, April 1994.  (Postscript)   
Reprinted in Selected Papers from 25 Years of ISCA, pages 485-496, August 1998.