CDA3103 - Computer Logic and Organization

Summer 2014

Class description: Functional overview of computer systems, interconnection of basic components, system performance measures, instruction set design, arithmetic logic unit, control unit, memory system, pipelining, interrupts and input-output.
Instructor: Mr. Saad Ahmad Khan
Teaching Assistants: Mr Junyao Zhang (
Office Hours: Wed 4:00pm - 5:00pm (in HEC-231)
Office: HEC - 315
Phone: (on last resort)
E-mail: (preferred means of communication)
Web Site:
The assignments and the other announcements will be posted on the course web site
Classroom: HPA1-0116
Class Hours: Monday, Wednesday 12:00 PM - 1:50PM
Office Hours: Monday, Wednesday 2:30PM - 4:00PM (in HEC-315)
Pre-requisites: Some familiarity with computer science
Credit Hours: 3 (3, 1)

Computer Organization and Design, Fifth Edition: The Hardware/Software Interface
Author(s) : Patterson & Hennessy

Computer Architecture (From Microprocessor To Supercomputers)
Author(s) : Behrooz Parhami

Acknowledgements: Thanks to Dr. Dan Garcia for his awesome slides on Computer Organization and Design.
Course Goals: 1. Introduce fundamentals of the organization and design of computers from both the computer
programmer's perspective and computer ''architect's'' perspective.
2. Cover the five basic components of a computer (input, output, memory, datapath, and control),
functions of each component, and how components interact with each other and with the software
systems they enable.
3. Learn Assembly Language through programming projects.
4. Explain memory hierarchy, cache, and addressing schemes.
5. Introduce hardware design of processor’s control and datapath, including pipelining concepts.
Grading: Homeworks (HW) : 25%, Programming Projects (PR) : 10%
Midterm-I: 20%, Midterm-II: 15%, MidtermFinal: 30%. Grading formula:
        HW = (HW1 + HW2 + HW3 + ...+ HWn) / n
        Pr = (Pr1 + Pr2 + Pr3 + ...+ Prn) / n
        Overall = 0.25 * HW + 0.10 * PR + 0.2 * Midterm1 + 0.15 * Midterm2 + 0.30 * Final
HW2, PR2 etc are exactly the number you got, so if you got 112, that is what you put in.
Standard 90/80/70/60 scale will be used for final grades (curved if necessary).

Makeup Exam Policy: No makeup exam or quiz will be given except for University pre-approved functions or activities. Student must provide advance written notification.
Integrity: All the quizzes, homeworks, and exams are individual work.
The division, college, and University are committed to honesty and integrity in all academic matters. We do not tolerate academic misconduct by students in any form, including cheating, plagiarism and commercial use of academic materials. Please consult the Golden Rule Handbook for the procedures which will be applied.

Syllabus (Tentative)

Topics [Lecture Notes & Readings]
May 12
Combinational Digital Circuits - I [Part 1] [Part 2]
May 14
Combinational Digital Circuits - II [Multiplexers] [Decoders] [Controlling Gates] Homework 1 [Due 5/21]
May 19
Digital Artihmetic [Number Systems] [Adders & Subtractors] [ALU] [Multipliers]
May 21
Digital Circuits with Memory - I [Flip-Flops] [Memory Design] Homework 2 [Due 5/28]
May 26
Memorial Day
[Official Holiday] No Class
May 28
Midterm Exam I

June 02
MIPS ISA Instruction Format [Assembly-Language] [MIPS-ISA]
Reading [2.1, 2.2, 2.3, 2.5, 2.6]
Project 1 [Due 6/15]
June 04
MIPS ISA (Conditional Statements, Loops) [MIPS-ISA II]
Reading [2.7, 2.10]
Homework 3 [Due 6/11]
June 09
MIPS ISA (Stacks, Functions) [Procedures and Stacks]
Reading [2.8, 2.13, 2.14]

June 11
Program Translation and CPU Performance [Program Translation] Reading [2.12, 2.20], [Performance] Reading [1.6, 1.7] Project 2 [Due 6/30]
Homework 4 [Due 6/18]
June 16
Number Representation, Floating Point Numbers, Multipliers and Dividers [Number Representation] [Floating Point Numbers]
[Multipliers and Dividers] Reading [3.1 - 3.5]

June 18
Logic Design, Flip Flops [Logic Design] [Flip-Flops] Reading [Appendix B.8, B.10, B.11]
June 23
Midterm Exam II

June 25
Memory Hierarchy (Main memory concepts)[Main memory concepts and Cache] [DirectMap Cache Example] Reading [5.1, 5.2, 5.3][Appendix B.9]
June 30 Cache Performance and Set Associative Cache [Cache Performance and Set Associative Cache] [Summary Flowchart] Reading [5.3, 5.4, 5.5]
July 02
Virtual Memory and Paging [Virtual Memory] Reading [5.7, 5.8] Homework 5 [Due 7/20]
July 07
Revision Class [DirectMap Cache and Set-associative Cache] [Numericals]
July 09
Single-Cycle Data Path [SingleCycle DataPath] Reading [4.1, 4.2, 4.3]
July 14
CPU Control [CPU Control] Reading [4.4]
July 16
Pipelining concepts, datapath and hazards [Pipelining Concepts] Reading [4.5, 4.6, 4.7]
July 21
Pipelined Datapath & Control[Pipelining Concepts and Parallelism]Reading [4.8, 4.10, 6.1, 6.2, 6.3, 6.5] Homework 6 [Due 7/26]
July 23
Revision Class
July 28
Final Exam Prep Q/A Session
July 30
Final Exam (Comprehensive)
Time: 12:00pm - 3:00pm