Huiyang Zhou (周辉阳)

(I am currently on leave at ECE department, North Carolina State University)
Associate professor

School of Electrical Engineering and Computer Science

University of Central Florida
4000 Central Florida Blvd
PO Box 162362
Orlando, FL 32816-2362

Office: ENG3 243

Tel: 407-823-5210
Fax: 407-823-5419

Email: zhou AT cs.ucf.edu

Education

2003 - Ph.D. in Computer Engineering, North Carolina State University, USA

1998 - M.E., National University of Singapore, Singapore

1995 - M.E., Xian Jiaotong University, P. R. China

1992 - B.E., Xian Jiaotong University, P. R. China

Research Interests

Computer architecture with special interests in high-performance microarchitecture, low-power architecture, DSP architecture, media processing architecture, GPGPU, architectural support for reliability, architectural support for security, back-end compiler design, code optimization, interaction between compilers and computer architecture, and embedded systems.

Students

Jingfei Kong

Ping Xiang

Yi Yang

Zhaoshi Zheng

Lin Cao

Alumni

Hongliang Gao PhD’08, 2008-09 Award of Outstanding Dissertation, College of Engineering and Computer Science. (First job: Intel Corp., Hillsboro, OR)

Martin Dimitrov, PhD’10 (First job: Intel Corp., AZ)

Yi Ma (M.S.) (Facebook, CA)

Teaching

ST: CDA 6938 Multi-core/Many-core Architectures and Programming

CDA5106 Advanced Computer Architecture I

CDA4150 Computer Architecture

Refereed Publication

Y. Yang, P. Xiang, J. Kong, and H. Zhou, “A GPGPU Compiler for Memory Optimization and Parallelism Management”, to appear in the ACM SIGNPLAN 2010 Conference on Programming Language Design and Implementation (PLDI’2010), June, 2010.
M. Dimitrov and H. Zhou, “Anomaly-based Bug Prediction, Isolation, and Validation: An Automated Approach for Software Debugging”, The 14^th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS-XIV), Mar. 2009. (The automated debugging tool can be downloaded here) (talk given at ASPLOS-XIV).
M. Dimitrov, M. Mantor, and H. Zhou, “Understanding Software Approaches for GPGPU Reliability”, The 2^nd workshop on General-Purpose Computation on Graphics Processing Units (GPGPU-2), to be held with the 14^th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS-XIV), Mar. 2009. (talk given at GPGPU2)
Jingfei Kong, Onur Acıiçmez, Jean-Pierre Seifert and Huiyang Zhou, “Hardware-Software Integrated Approaches to Defend Against Software Cache-based Side Channel Attacks”, The 15^th International Symposium on High Performance Computer Architecture (HPCA-15), Feb., 2009. (talk)
M. Dimitrov and H. Zhou, “Combining Local and Global History for High Performance Data Prefetching”, The 1^st Journal of Instruction-Level Parallelism (JILP) Data Prefetching Championship (DPC-1), to be held with 15^th International Symposium on High Performance Computer Architecture (HPCA-15), Feb., 2009. (ranked 2^nd) (talk, code)
J. Kong, O. Acıiçmez, J.-P. Seifert and H Zhou, “Deconstructing New Cache Designs for Thwarting Software Cache-based Side Channel Attacks”, The 2^nd ACM Computer Security Architecture Workshop (CSAW-2), held in conjunction with 15th ACM Conference on Computers and Communication Security (CCS-2008), pp. 25-34, Oct. 2008. (talk given at CSAW-2)
H. Gao, Y. Ma, M. Dimitrov, and H. Zhou, “Address-Branch Correlation: A Novel Locality for Long-Latency Hard-to-Predict Branches”, The 14^th International Symposium on High Performance Computer Architecture (HPCA-14), pp. 74-85, Feb., 2008. (talk given at HPCA-14)
M. Dimitrov and H. Zhou, “Unified Architectural Support for Soft-Error Protection or Software Bug Detection”, International Conference on Parallel Architectures and Compilation Techniques (PACT’07), pp. 73-82, Sept. 2007. (talk given at PACT’07)
H. Gao and H. Zhou, “PMPM: Prediction by Combining Multiple Partial Matches”, Journal of Instruction-Level Parallelism (JILP), pp. 1-18, Vol. 9, 2007.
Y. Ma, H. Gao, M. Dimitrov, and H. Zhou, “Optimizing Dual-Core Execution for Power Efficiency and Transient-Fault Recovery”, IEEE Transactions on Parallel and Distributed Systems, vol. 18, no. 8, pp. 1080-1093, Aug., 2007
H. Gao and H. Zhou, “PMPM: Prediction by Combining Multiple Partial Matches”, 2^nd Championship Branch Prediction (CBP-2) held with the 39^th International Symposium on Microarchitecture (MICRO-39), pp. 19-24, Dec. 2006. (finalist in both the realistic and idealistic tracks, code for the realistic track, code for the idealistic track, talk given at CBP-2)
M. Dimitrov and H. Zhou, “Locality-based Information Redundancy for Processor Reliability”, 2^nd Workshop on Architectural Reliability (WAR-2) held in conjunction with 39^th International Symposium on Microarchitecture (MICRO-39), pp. 29-36, Dec. 2006. (presentation given at WAR-2)
J. Kong, C. Zou, and H. Zhou, “Improving Software Security via Runtime Instruction-Level Taint Checking”, Workshop on Architectural and System Support for Improving Software Dependability (ASID) held in conjunction with 12^th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS-XII), pp. 18-24, October, 2006. (presentation given at ASID’06)
Y. Ma and H, Zhou, “Efficient Transient-Fault Tolerance for Multithreaded Processors Using Dual-Thread Execution”, IEEE International Conference on Computer Design (ICCD), pp. 120-126, October, 2006. (presentation given at ICCD’06)
Y. Ma, H. Gao, and H. Zhou, “Using Indexing Functions to Reduce Conflict Aliasing in Branch Prediction Tables”, IEEE Transactions on Computers (TC), pp. 1057-1061, August, 2006.
H. Zhou, “A Case for Fault Tolerance and Performance Enhancement using Chip Multi-Processors”, IEEE Computer Architecture Letters (CAL), pp. 1-4, Sept. 2005.
H. Zhou, “Dual-Core Execution: Building a Highly Scalable Single-Thread Instruction Window”, Proceedings of the 2005 International Conference on Parallel Architectures and Compilation Techniques (PACT’05), pp. 231-242, Sept. 2005. (presentation given at PACT’05)
H. Gao and H. Zhou, “Adaptive Information Processing: An Effective Way to Improve Perceptron Branch Predictors”, Journal of Instruction-Level Parallelism (JILP), pp. 1-10, Vol. 7, 2005.
H. Zhou and T. M. Conte, “Enhancing Memory-Level Parallelism via Recovery-Free Value Prediction”, IEEE Transactions on Computers (TC), pp. 897-912, July 2005.
H. Gao and H. Zhou, “Adaptive Information Processing: An Effective Way to Improve Perceptron Branch Predictors”, Champion, In the 1^st Championship Branch Prediction (CBP-1) held with the 37^th International Symposium on Microarchitecture (MICRO-37), Dec. 2004. (presentation, download the code, the simulation framework).
H. Zhou, M. Toburen, E. Rotenberg, and T. M. Conte, "Adaptive Mode Control: A Static-Power-Efficient Cache Design", ACM Transactions on Embedded Computing Systems (TECS), pp. 347-372, vol. 2, no. 3, August, 2003.
H. Zhou and T. M. Conte, "Enhancing Memory Level Parallelism via Recovery-Free Value Prediction", The 2003 International Conference on Supercomputing (ICS'03), pp. 326-335, June 2003.
H. Zhou, J. Flanagan, and T. M. Conte, "Detecting Global Stride Locality in Value Streams", The 30^th ACM/IEEE International Symposium of Computer Architecture (ISCA-30), pp. 324-335, June 2003.
H. Zhou and T. M. Conte, "Code Size Efficiency in Global Scheduling for ILP Processors", The 6^th Annual Workshop on Interaction between Compilers and Computer Architectures (INTERACT-6) held in conjunction with HPCA-8, pp. 79-90, February 2002.
H. Zhou, M. Toburen, E. Rotenberg, T. M. Conte, "Adaptive Mode Control: A Static-Power-Efficient Cache Design", Proceedings of the 2001 International Conference on Parallel Architectures and Compilation Techniques (PACT'01), pp. 61-70, Sept. 2001.
H. Zhou, M. D. Jennings, T. M. Conte, "Tree Traversal Scheduling: A Global Scheduling Technique for VLIW/EPIC Processors", The 14th Annual Workshop on Languages and Compilers for Parallel Computing (LCPC'01), LNCS 2624, pp. 223-238, Springer Verlag, August, 2001 (2003).
A. A. Kassim, H. Zhou, S. Ranganath, Automatic IC orientation checks, Machine Vision and Applications, pp. 107-112, Vol. 12, No. 3, pp. 107-112, 2000.
H. Zhou, A. A. Kassim, S. Ranganath, A fast algorithm for detecting die extrusion defects in IC packages, Machine Vision and Applications, pp. 37-41, Vol.11, No.1, pp.37-41, 1998.
Zhou Huiyang, Qu Liangsheng, Li Aihua, Test Sequencing and Diagnosis in Electrical System with Decision Table, Microelectronics and Reliability, Vol.36, No.9, pp.1167-1175, 1996.

Refereed Educational Publication

H. Gao, M. Dimitrov, J. Kong, and H. Zhou, “Experiencing Various Massively Parallel Architectures and Programming Models for Data-Intensive Applications”, Workshop on Computer Architecture Education (WCAE-08), held in conjunction with ISCA-35, 2008. (talk given at WCAE-08)

Technical Reports

H. Zhou, "Code size aware compilation for real-time applications", Technical Report, CS department, University of Central Florida, July 2003.
H. Zhou and T. M. Conte, "Performance modeling of memory latency hiding techniques", Technical Report, ECE Department, N. C. State University, January 2003.
H. Zhou and T. M. Conte, “Using Performance Bounds to Guide Pre-scheduling Code Optimizations”, Technical Report, ECE Department, N. C. State University, Sep. 2002.
M. D. Jennings, H. Zhou, T. M. Conte, "A Treegion-based Unified Approach to Speculation and Predication in Global Instruction Scheduling", Technical Report, ECE Department, N. C. State University, August 2001.
H. Zhou, C. Fu, E. Rotenberg, T. Conte, "A study of value speculative execution and mispeculation recovery in superscalar microprocessors", Technical Report, ECE Department, N. C. State University, Jan., 2001.
H. Zhou, M. Toburen, E. Rotenberg, T. Conte, "Adaptive Mode Control: A Low-Leakage Power-Efficient Cache Design", Technical Report, ECE Department, N. C. State University, Nov., 2000.

Recent Funding

PI, National Science Foundation (NSF) CAREER: Architectural Support for Automated Software Debugging. (2008-2013) $400,078 + $54,158 (Project website)
PI, National Science Foundation (NSF) TC: Medium: Collaborative Research: Side-Channel-Proof Embedded Processors with Integrated Multi-Layer Protection (2009-2011) $100,000
PI, GPGPU@UCF, AMD, (2008-2010) $170,000 + $70,000

Recent Professional Service

Editorial Board, Journal of Instruction-Level Parallelism (JILP)
Associate Editor, ACM Transactions on Architecture and Code Optimization (ACM TACO)