EEL 5722C - Field-Programmable Gate Array (FPGA) Design

fpga

Welcome to the EEL 5722C Course Home Page! This serves as the syllabus for the course.

Instructor: Mingjie Lin, Assistant Professor (HEC-416), Department of Electrical and Computer Engineering, tel: 407-882-2298, email: mingjie@eecs.ucf.edu Office Hours : Mon/Wed 10:15am-noon

TA: Rakan Khraisha (rakan784@knights.ucf.edu)

Time and Locations: Lecture: Mo, We 9:00AM-10:15AM @ BA-0209
Lab1: Mo 3:00PM-5:50PM @ ENGR-0257; Lab2: Mo 6:00PM-8:50PM @ ENGR-0257.

Course Description

    Recent advances in VLSI technology have enabled a new class of application-specific computer architectures that take advantage of application-level parallelism. These reconfigurable computers can be quickly customized at the hardware level to perform exactly the computation required in hardware, overcoming the fixed hardware configurations found in many contemporary microprocessors.

    EEL5722 focuses on the most popular reconfigurable computing platform--FPGA. Its main course components include FPGA architectures, design flow, technology mapping, placement, routing, reconfigurable computing applications, and evolvable hardware. The overall objective is to study FPGA's history and its technology evolution, investigate the state-of-the-art FPGA-based reconfigurable computing both from a hardware and software perspective, and explore potential research opportunities of FPGA computing. To this end, we first review in detail the basic building blocks of field-programmable gate arrays (FPGAs). Second, we focus on the architecture for existing multi-FPGA systems and on compilation techniques for mapping applications described in a hardware description language to reconfigurable hardware. Finally, specific contemporary reconfigurable computing systems are examined to identify existing system limitations and to highlight opportunities for research. (3 credits)

Prerequisites:

    EEL 3342C (Introduction to Digital Circuits and Systems) is prerequisite for this class. Experience in computing architecture and organization may be helpful in understanding some of the course material but is not required.

Grading: 

    Lab Assignments (40%), Mid-Term Exam (30%), Design Projects and Presentation (30%).

Honesty Policy:

    Consultation with fellow students is encouraged, especially on design issues. However, directly copying another student's work defeats the purpose of the assignments and is an honor code violation. All written assignments should be original work. Portions of written work that are taken word-for-word from other authors (students or researchers) will be assigned a failing grade and may result in a failing grade in the course.

Computer Requirements:

    On-campus students will be doing labs using CAD software on UNIX workstations and PCs.

Course text:

Reference Material: 

    Research papers and book chapters will be suggested reading for each class to help stimulate discussion. More Xilinx FPGA background information can be found on this page.

Lab Projects : There will be five lab assignments that involve the development and use of CAD tools for FPGA applications. Specifically,

       * Final Design Project: To be determined

Course Philosophy : My goal is for students to understand the FPGA technology in depth and become familiar with the state-of-the-art in reconfigurable computing. During the course open research problems in the field will be noted and students will have the opportunity to begin preliminary investigation of these issues through classroom projects.

Schedule (minor changes possible throughout the semester )

Event Spring 2011 Topics Notes Supplementary Reading
Lecture 1 Jan 10 Introduction (Objectives, Expectations, Logistics), FPGA's History and Future pdf Q1 Chap 1-2
Lecture 2 Jan 12 FPGA Architecture I: Overall concept and programming methods pdf Q1 Chap 3, Verilog Tutorial
MLK day Jan 17
Lecture 3 Jan 19 An Introduction to HDL (Verilog and VHDL) pdf Verilog vs. VHDL
Lecture 4 Jan 24 FPGA Architecture II & III: LUT & Routing Arch. pdf 1. Shannon's paper  "The Synthesis of Two-Terminal Switching Circuits" (bstj.bell-labs.com/BSTJ/images/Vol28/bstj28-1-59.pdf) (very large pdf file, only link is provided.)

2. Optimizing Sequential Cycles Through Shannon Decomposition and Retiming

3. The synthesis of sequential switching circuits - Huffman
Lecture 5 Jan 26 FPGA CAD I:   Technology Mapping pdf Note: These reading materials are NOT required, but can be very useful for those of you who want to get deeper into the course material and look for research topics.

J. Cong, Y. Ding, Combinational
Logic Synthesis for LUT Based Field Programmable Gate Arrays, (60 pages). Tutorial and survey paper on FPGA synthesis. ACM Trans. on Design Automation of Electronic Systems (TODAES), April 1996.

B. Wurth et al. Functional Multiple-Output Decomposition with Application to Technology Mapping for Lookup Table based
FPGAs, TODAES, July 1999.

N. Vemuri, P. Kalla, R. Tessier, BDD based Logic Synthesis for LUT-based FPGAs, (28 pages). TODAES ,2000.

Improving Simulated Annealing-Based FPGA Placement With Directed Moves

Improving FPGA Placement With Dynamically Adaptive Stochastic Tunneling

Parallelizing Simulated Annealing-Based Placement Using GPGPU

FPGA Placement and Routing Using Particle Swarm Optimization

Hardware-assisted simulated annealing with application for fast FPGA placement

Fast Maze Router

VPR- Routing Algorithm Design
Lecture 6 Jan 31
Lecture 7 Feb 2 FPGA CAD II:  Placement pdf, hw
Lecture 8 Feb 7 pdf, hw
Lecture 9 Feb 9 FPGA CAD III: Routing pdf, hw
Lecture 10 Feb 14 pdf, hw
Lecture 11 Feb 16 FPGA Modern Application and Its Potential pdf
Lecture 12 Feb 21 Logic Emulation and Computer Architecture Research Accelerator pdf
Lecture 13 Feb 23 pdf RAMP: A Research Accelerator for Multiple Processors
Lecture 14 Feb 28 Mid-term prep.: All homework problems + Old mid-term exam solutions
Lecture 15 Mar 2 Mid-term Exam (reminder: withdrawal deadline ends at 11:59 p.m. of Friday, March 4)
 old mid-term of 2008. Caution: This exam does NOT in any way indicate the scope of our exam. The course material in 2008 is quite different from our lectures. 
Spring Break Mar 7
Mar 9
Lecture 16 Mar 14 FPGA Computing --- Big picture and User/Language Level (HDL, Verilog, VHDL, ...), cont. pdf
Lecture 17 Mar 16 FPGA Computing --- Abstraction Level: DSP applications, Embedded Cores pdf
Lecture 18 Mar 21 pdf
Lecture 19 Mar 23 FPGA Computing --- Chip Level (Reconfigurable Computing Architectures) pdf
Lecture 20 Mar 28 Final Project --- JPEG Decoder and Huffman Compression pdf
Lecture 21 Mar 30 Final Project --- Huffman Algorithm and source code structure pdf
Lecture 22 Apr 4 Advanced FPGA Techniques: Crossing Clock Domains pdf
Lecture 23 Apr 6 Emerging FPGA technology: Structured ASICs pdf
Lecture 24 Apr 11 FPGA Timing Issues and Their Standard Solutions 
pdf
Lecture 25 Apr 13 C-to-Gates and High-level language FPGA programming pdf
Lecture 26 Apr 18 Hardware/Software Co-Design  pdf
Lecture 27 Apr 20 The Future of FPGA technology and Its Potential
pdf
Lecture 28 Apr 25 Course Wrap-up  pdf

Lab Schedule

Event Spring 2011 Topics Assignments Pre-Study Suggestions Pre-study + Supplementary Readings
Lab 1 Jan 24, Jan 31 Design and implement a decimal push button counter pdf 1. Download Xilinx ISE Webpack and install on your own computer.
2. Following ISE Quick Start Tutorial and play with ISE.
3. Choose a simple HDL example (either in Verilog or VHDL), and try simulating its functionality by following ISE Simulator (ISim) In-depth Tutorial.
4. Read XUPV2P Documentation to get familiar with the device used in the lab.		 1. XUPV2P Documentation (link)
2. XUPV2P Reference Designs (link)
3. ISE WebPACK Design Software (link)
4. ISE Simulator (ISim) In-depth Tutorial (link)
5. ISE Quick Start Tutorial (link)
Lab 2 Feb 7, Feb 14  Display color on a VGA monitor pdf 1. Lab2 tutorial (link)
Lab 3 Feb 21, Feb 28, Input from a PS/2 keyboard pdf 1. Lab3 tutorial (link)
Lab 4 Mar 7, Mar 14  Display PS/2 keyboard input on a VGA monitor pdf 1. Lab4 tutorial (link)
Lab 5 Mar 21, Mar 28 Display an image on a VGA monitor pdf 1. Lab5 tutorial (link)

Final Project


Other information

tessier 'at' ecs.umass.edu (Last Update: 7/09/04)