Homework 3.

Due: Wednesday, November 8th, 2006
Submission: By plain text e-mail to lboloni@eecs.ucf.edu.
            In the subject write: EEL 5708, HW 3
            
            Do not send other correspondence with the homework. Send it in a 
            separate mail, with appropriate subject line. E.g.: question about
            problem 4. 

 
1. Suppose that a processor with a load/store architecture executes at a clock
rate of 1GHz, with the ideal CPI of 1.2. Profiling shows that 15% of the
instructions in average are load or store instructions. The processor accesses the
memory through a separate data and instruction cache. An average 2% of the
instructions produce an instruction miss, while 12% of the data accesses are
cache misses. The penalty of a miss is 140 cycles. Cache hits do not produce
any penalty. 

(a)	What is the real CPI of the architecture?
(b)	What is the average memory access time (AMAT) of the architecture?

2. Read the paper "Clock Rate versus IPC: The End of The Road for Conventional
Microarchitectures" by Vikas Agarwal, M.S. Hrishikesh, Stephen W. Keckler and
Doug Burger. Summarize it in 500 words.

3. Read the paper "Hitting the Memory Wall: Implications of the Obvious" by
Wm. A. Wulf and Sally A. McKee. Summarize it in 500 words.