Homework 2.

Due: Friday, October 6th, 2006
Submission: By plain text e-mail to lboloni@eecs.ucf.edu.
            In the subject write: EEL 5708, HW 2
            
            Do not send other correspondence with the homework. Send it in a 
            separate mail, with appropriate subject line. E.g.: question about
            problem 4. 


1. Consider the following assembly program written for a RISC style 32 bit 
machine:

   ld  r20, 16000     # load immediate
   ld  r19, 20000  
   ld  r18, 40000    
start:
   add r3, r20, r19
   ld  r1, 0(r3)      # load into r1 from memory
   add r4, r20, r18
   ld  r2, 0(r4)
   mult r2, r1, r2
   st  0(r4), r2      # store r2 into memory
   ld  r2, 4
   sub r20, r20, r2   
   bnez r20, start    # jump to start if r20 not equal with zero
   
  a) Write a C, C++ or Java program which corresponds to this assembly level 
  program.
  
  b) Identify the RAW, WAR and WAW which can appear in the program conflicts 
  in the program.
  
  c) Assume that the program is run on a machine which has a 5 stage pipeline. 
  Rewrite the program by inserting "nop" operations where there will be stalls.  
  
  d) Would a processor with a Tomasulo-style register renaming improve the
  execution time of this program? What about the speculation? Superscalar?
  Which one would perform better, the original version or the unrolled?
  Explain. 
  
  e) Unroll the loop in the program 4 times in software (assembly). 
  Transform the program by register renaming such that the number of stalls 
  is minimized.  

2. Assume a processor with a 5-stage pipeline. Assume an instruction mix of 10%
load and store instructions, 10% conditional branches, 80% arithmetic and logic
instructions. 
   (a) Assume that the load and store instructions stall the pipeline for 4
   cycles, while the conditional branches for 3 cycles. What will be the CPI of
   the processor?
   (b) Assume that we introduce a branch prediction system, which always
   predicts branch not taken. It turns out that in the real applications 60% of the
   branches are taken. In case of misprediction, the processor still stalls for 3 cycles. 
   What will be the CPI of the processor? 
  
3. Read the articles about the MIPS architecture from the class webpage (Sept 6
entry). Write a summary of the MIPS architecture in 500 words.
  
4. Read the paper "Implementing precise interrupts in pipelined processors",
by J.E.Smith and A.R. Pleszkun. Summarize it in 500 words.