CDA 5106 Advanced Computer Architecture

Fall 2015

Time: Monday and Wednesday 6:00-7:15 PM

Place: HEC 0117



Instructor: Dan C. Marinescu

Office hours: Monday and Wednesday:

5:00-6:00 in HEC 304


TA: Ramya Pradhan

Office Hours:



Title: Computer Architecture; A Quantitative Approach (5th Edition)

Authors: John Hennessy and David Patterson

Publisher: Morgan Kaufmann 2012


     A Instruction Set Principles

     B Memory Hierarchy

     C Pipelining

     D Storage Systems

     E Embedded Systems

     F Interconnection Networks

     G Vector Processors

     H Hardware and Software for VLIW and EPIC

     I Large-Scale Multiprocessors and Scientific Applications

     J Computer Arithmetic

     K Survey of Instruction Set Architectures

     L Historical Perspective


Chapter Presentations

Chapter 1

Chapter 2

Chapter 3

Chapter 4

Chapter 5

Chapter 6

Additional References



A.  General Information


         Class objective: Familiarize the graduate students with the modern architecture of processors, as well as, large-scale systems used in data centers, the so-called Warehouse Scale Computers (WSCs). Present in depth concepts related to instruction-, data-, thread-, and request-level parallelism necessary for understanding

o    a. Program and application optimization

o    b. Architectural support for multi-media applications

o    c. Real-time and embedded application design and implementation

o    d. Organization of large-scale computing systems

         Student participation

o    A component of the grade is based on class presentations.

  Students will form groups of two or three.

  Each group will make two 20 minutes presentations according to the schedule listed in Section D.

  Each presentation should be made in Powerpoint and turned-in before the presentation.

  Student presentations will start in week 2 on Wednesday September 2 at the rate of two per session. A bonus will be given to the students presenting in weeks 2 and 3.

  The schedule of presentations is listed in Section D of this web page.

o    A presentation should include a review of the main ideas in one of the papers related to the topic. Read carefully the appendix designated as required reading and identify the paper you wish to discuss as one of the papers cited either in the appendix or in the book chapter.

o    Part of your grade will be based on class participation. Participation includes, but it is not limited to: class attendance, asking questions, and participation in discussion during the lectures and students presentations.

o    Homework assignments: there will be 5 homework assignments each consisting of 2-3 problems from the textbook.

o    Project: a class project will be assigned during week 5 and will be due Monday. November 13, 2015, before the class.

o    Reading assignments are mandatory for understanding the material presented in class.

         After each class the slides covering the material presented in class as well as additional material will be posted.

B.   Grade assignment

Grade distribution: The weights of different contributions to your grade:

         20% First Presentation

         20% Second Presentation

         20% Class Participation

         15% Homework

         25% Project

Cheating: You will work with one or two others students for the presentations. The presentation should be original, citations for sources are mandatory. The homework and the project must be your own, you are not allowed to reproduce the results of any of your colleagues, or results obtained from any other source. The minimum penalty for cheating includes:

  1. An automatic zero on the assignment
  2. Reduction of your final grade by one letter grade;
  3. Notification of the incident to the UCF Office of Student Conduct.

More information about rules and regulations au UCF can be found at


C.Topics covered


Chapter 1 Quantitative Design and Analysis


2.Classes of computers

3.Trends in computer architecture


5.Power and energy

6.Chip fabrication costs


8.Principles of computer design

9.Fallacies and pitfalls

10.                Evolution of supercomputers

11.                Problem solving


Chapter 2 Memory Hierarchy Design

1.Memory hierarchy

1.Basic concepts

2.Design techniques


1.Types of caches: Fully associative, Direct mapped, Set associative

2.Ten optimization techniques

3.Main memory

1.Memory technology

2.Memory optimization

3.Power consumption

4.Memory hierarchy case studies: Opteron, Pentium, i7.

5.Virtual memory

6.Problem solving


Chapter 3 Instruction-Level Parallelism (ILP)

1.Pipelining; hazards

2.ILP - data, name, and control dependence

3.Compiler techniques for exposing ILP:

1.Pipeline scheduling,

2.Loop unrolling,

3.Strip mining,

4.Branch prediction

4.Register renaming

5.Multiple issue and static scheduling


7.Energy efficiency


9.Fallacies and pitfalls

10.                Problem solving


Chapter 4 Data-Level Parallelism

1.SIMD architecture

2.Vector architectures optimizations:

1.Multiple Lanes,

2.Vector Length Registers,

3.Vector Mask Registers,

4.Memory Banks,



3.Programming Vector Architectures

4.SIMD extensions for media apps

5.GPUs Graphical Processing Units

6.Fermi architecture innovations

7.Examples of loop-level parallelism



Chapter 5 Thread-Level Parallelism


2.Centralized SMA shared memory architecture

3.Performance of SMA

4.DMA distributed memory architecture


6.Models of Consistency


Chapter 6 Request-Level and Data-Level Parallelism

1.Cloud computing basic concepts

2.Request-level parallelism and WSCs (Warehouse Scale Computers).

3.Programming models MapReduce

4.WSC architecture

5.Energy-proportional systems

6.Scientific applications and WSC

7.Cloud computing


Section D


Class Schedule Lecture slides and student presentation schedule

Student groups