Computer Engineering Colloquium

To manage the design of future billion-transistor microprocessors, it is important to quickly narrow architectural choices to a few promising designs. Architecture evaluations are traditionally carried out on timing simulations. Although they are detailed and accurate, such simulators are slow and do not consider the target semiconductor technology.

In this talk, I will present an early stage analytical model for architecture evaluations. This method is several orders of magnitude faster than timing simulators. The model captures architecture structure, semiconductor technology properties, and application behavior through numerical parameters. It uses these parameters to determine architectural performance, potential bottlenecks in a design, and the impact of semiconductor technology on system speed. I will also describe a method to evaluate various forms of software parallelism that can be used to choose an optimum architecture for any given application. Because of their speed, these methods are useful for fast architecture design space explorations in early design stages.

Tarek Taha is currently a Ph.D. candidate in the Electrical and Computer Engineering Department at Georgia Institute of Technology in Atlanta. He received both his Bachelor and Master of Electrical Engineering from Georgia Tech. His research interests include computer architecture modeling, VLSI design and modeling, architectures for gigascale integration, embedded systems, architectural power modeling and the impact of interconnects on architectures.