CGS 3269 - COMPUTER SYSTEMS ARCHITECTURE
SUMMER 2002
COURSE SYLLABUS
This page last updated:Tuesday, July 23, 2002 17:27
Details about the Class Presentations can be found here.
Important Dates:
July 04: Holiday
July 09, 11, 16, 18: Class Presentations
July 23: Revision for the Final Exam
July 25: Final Exam
Class Meets: Tuesday & Thursday at 12:00-1:50 pm in ENGR2 302
Instructor
Vivek Bhatia
http://www.cs.ucf.edu/courses/cgs3269
Office Hours:
Office - Computer Science Building,
CSB 207
Monday |
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Tuesday |
2 PM - 3 PM |
Wednesday |
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Thursday |
2 PM - 3 PM |
Friday |
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TA
Feixue (Stephanie) Han
Email: fhan@cs.ucf.edu
Office Phone: 407-823-4733
Office Hours: CSB 207, Wednesday 1 PM - 2 PM
Grades
None yet, but I grade on a curve.
Grade |
A |
B |
C |
D |
F |
Guaranteed | > 90 | > 80 | > 70 | > 60 | < 60 |
Last Offering | 36 | 59 | 7 | 2 | 6 |
Grading
Homework/Assignments | 20% |
In-class Quizzes | 20% |
Mid-term Exam | 25% |
Cumulative Final Exam | 25% |
Attendance/Class Participation | 10% |
Notes
Text: Structured Computer Organization, Fourth Edition, Andrew S. Tanenbaum, Prentice Hall, ISBN 0-13-095990-1
Course Topics
COURSE TOPICS |
CLASS NOTES |
General overview of various architecture designs Five basic components of the PC architecture: CPU, memory, I/O, disk storage, programs Number systems: binary, octal, hexadecimal, and decimal Binary and Hex arithmetic |
classnotes1 |
Internal information - How data is stored in the PC Character representations in PCs, ASCII and Unicode |
classnotes2 |
In-class Quiz |
May 14,2002 |
Transistors, gates, half adders, full adders The architecture of the PC Brief history of the evolution of various PC components Buses, BIOS, and motherboards |
classnotes3 |
Microprocessors CISC vs. RISC Architectures Superscalar speedup, pipelined FPUs, ALUs Micro-code, L1 and L2 Cache memory DMA channels, Internal clock speeds Chip fabrication technology and its evolution |
classnotes4 |
Internal Memory RAM, ROM - erasable, programmable, erasable and programmable RAMBUS Technology Cache memory, direct-mapped, set-associative, fully-associative Cache memory address resolution, Cache memory replacement policies |
classnotes5 |
MID-TERM EXAM |
06/13/2002 |
Error detection and correction in memory Hamming codes, SECDED codes External Memory (Disk storage and other storage media) RAID technology (Redundant Array of Inexpensive Disks) |
classnotes6 |
Instruction set design, Types of instructions Addressing techniques, registers, boundary alignment Exception handling, interrupts |
classnotes7 |
Bus technology, Expansion buses, PCI, AGP, ISA, EISA, VL, etc. Data lines, addressing lines, multiplexing Bus control, mastering, timing, sharing, burst modes |
classnotes8 |
Introduction to other computer architectures Comparison of architectures, benchmarks, MIPS, FLOPS, MFLOPS Parallel processing, interconnection networks Pipelined processing SIMD architectures, MIMD architectures, stack machines Vector processors |
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Click here for the Boolean Algebra Rules
Assignments
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Specification |
Assigned Date |
Due Date |
Assignment # 1 |
assign1.html |
05/23/2002 |
06/04/2002 |