CDA 5106 - Advanced Computer Architecture I
READINGLIST

HISTORICAL PERSPECTIVES
1) Lavington, S. H., "The Manchester Mark I and Atlas: A Historical Perspective", Communications of the ACM, (21) 1, January 1978, pp. 4-12.
(01/23/02) Marcia Willians and Jon Catlett

2) Amdahl, G. M., Blaauw, G. A., and Brooks, F. P. Jr. "Architecture of the IBM System/360". IBM J. of Research and Development, 8(2), 1964, pp 87-101.
(01/23/02) Huy Truong and Derrick Sines

3) Hauck E.A., Dent B.A., "Burroughs B6500/6700 stack mechanism", AFIPS SJCC 1968, pp. 245-251.
(01/30/02) Yao Hua Ho and Ai Hua Ho


PIPELINE
4) Russell, R. M., "The CRAY-1 Computer System", Communications of the ACM, (21) 1, January 1978, pp. 63-72.
(01/30/02) Tho Ding and Gang Ning

FAULT TOLERANT
5) Katzman, J., "A Fault-Tolerant Computing System," In D. Siewioreck et al, editors, Computer Structures: Principles and Examples, chapter 29,McGraw-Hill,1982.
(02/04/02) Euripides Montagne


RISC/CICS
6) Emer, J.S. and Clark, D.W. "A Characterization of Processor Performance in the VAX-11/780", Proc. of 11th Annual Intl. Symposium on Computer Architecture, Ann Arbor, MI, May 1984, pp. 176-185.
(02/06/02) Shane Marcus and Eric Wayte

7) Bhandarkar, D. and Clark, D. W., "Performance from architecture: Comparing a RISC and a CISC with similar hardware organization". In Intl. Conf. on Architectural Support for Prog. Lang. and Operating Sys., ASPLOS-IV, Santa Clara, CA, Apr. 8-11, 1991, pp. 310-319.
(02/06/02) Abhishek Karnik and Rikartik Narayanan

DATA FLOW
8) J. Dennis, J. and Misunas, P.D., "A Preliminary Architecture for a Basic Data Flow Processor", Proc. Second Annual Symp. Computer Architecture, Houston, Tex., Jan. 1975, pp. 126-132.

( read this reference too: J. Dennis. "Data flow supercomputers". Computer, (13) 2, 1980, pp. 48-56.)
(02/13/02) Temitope Alo and Tai The Do

9) Gajski, D. A. Padua , D. A., Kuck, D. J., and Kuhn, R. H., "A second opinion on data-flow machines and languages". IEEE Computer, February 1982, pp. 58-69.
(02/13/02) Aamir Sutla and Mathew Lowery


SYSTOLIC ARRAYS
10) Kung. H.T. and Leiserson, C.E., "Algorithms for VLSI processor arrays". In C. Mead and L. Conway, editors, Introduction to VLSI Systems, chapter 8.3. Addison-Wesley, 1980.
(02/13/02) Daniel Schwarz and Andrew Pierro

VLIW
11) Fisher, J. "Very long instruction word architectures and the ELI-512". In Proc. 10th International Symposium on Computer Architecture, June 1983, pp. 140-150.
(02/20/02) Shakeel Anjum and Farhan Shamsi

SUPERSCALARS PROCESSORS
12) Smith, J.E. and Sohi, G.S., "The Microarchitecture of Superscalar Processors," Proceedings of the IEEE, vol. 83, Dec. 1995, pp. 1609-1624.
(02/20/02) Aleksey Gritsay and Balaji Chandrasekaran

RAID
13) Patterson, D., Gibson, G. and Katz, R., "A Case for Redundant Arrays of Inexpensive Disks (RAID)". Proceedings of the SIGMOD Conference, June 1988.
(02/27/02) Ering Hasting and Jaruwan Mesit

MEMS
***14) Operating System Management of MEMS-based Storage Devices. Griffin, J.L., Schlosser,
S.W., Ganger, G.R. and Nagle, D.F. Proceedings 4th Symposium on Operating Systems Design &
Implementation (OSDI 2000), San Diego, CA, October 23-25, 2000.

(read this reference too: MEMS-Based Integrated-Circuit Mass-Storage Systems. L. Richard Carley, Gregory R.Ganger and David F. Nagle. COMMUNICATIONS OF THE ACM November 2000, Vol.43, No.11.)
(02/27/02) Werapong Jiwawahanasak and Wattanee Viriyasitavat

PIM-IRAM
***15) Kogge, P. M., Brockman, J. B., Sterling, T. and Gao, G., "Processing in memory: Chips to petaflops". In Workshop on Mixing Logic and DRAM: Chips that Compute and Remember at ISCA '97. http://iram.cs.berkeley.edu/isca97-workshop/, Denver, CO, June 1997.
(03/06/02) Yaser Ajmal sheikh

16) David Patterson, Thomas Anderson, Neal Cardwell, Richard Fromm, Kimberly Keeton, Christoforos Kozyarakis, Randi Thomas, Katherine Yelik. A Case for Intelligent RAM: IRAM. In IEEE Micro, April 1997.

( read this reference too: C. Kozyrakis, S. Perissakis, D. Patterson, T. Anderson, K. Asanovic, N. Cardwell, R. Fromm, J. Golbus, B. Gribstad, K. Keeton, R.Thomas, N. Treuhaft, and K. Yelick. "Scalable processors in the billion-transistor era: IRAM." IEEE Computer, vol. 30, no. 9, pp. 75--78, September 1997.)
(03/06/02) Ahmed Koshak and Hamid Narachi

SINGLE-CHIP MULTIPROCESSORS
***17) K. Olukotun, B.A. Nayfeh , L. Hammond, K. Wilson, and K.-Y. Chang. "The Case for a Single-Chip Multiprocessor." In Proc. ASPLOS-VII, pp. 2-11 Oct. 1996.

CASE STUDY: Luiz André Barroso, Kourosh Gharachorloo, Robert McNamara, Andreas Nowatzyk, Shaz Qadeer, Barton Sano, Scott Smith, Robert Stets, Ben Verghese, Piranha: a scalable based on single-chip multiprocessing Proceedings of the 27th annual International Symposium on Computer Architecture 2000 Pages: 282 - 293.
(03/20/02) David Oger and Olivier Bagouet(both papers)

EPIC
***18) M. S. Schlanker, "EPIC: Explicitly Parallel Instruction Computing", Computer, vol. ?, No. ?, pp 37--45, 2000.

CASE STUDY: Jerry Huck et al., "Introducing the IA-64 Architecture", Sept - Oct. 2000, pp. 12-23
(03/20/02) Hong Yang, Liang Wang and Shuxin Li

EMERGING TECHNOLOGIES
***19) Leonard Adleman: Molecular computation of solutions to combinatorial problems. Science, 266:1021-1024. (Nov. 11). 1994.

(read this reference too: Leonard Adleman: Computing with DNA. Scientific American, 279(2):54--61, August 1998.)
(03/27/02) Namita Gogia and Yaser Sheikh

20) Michael T. Niemier and Peter M. Kogge, "Exploring and Exploiting Wire-Level Pipelining in Emerging Technologies", International Symposium of Computer Architecture, Sweden, July 2001. pp. 166-177 Pinnama Reddy Naveen and Raghunandan Pannala

Other important references:

MOORE'S LAW
Gordon E. Moore, "Cramming More Components Onto Integrated Circuits", Electronics, April 19, 1965

A. K. Uht, V. Sindagi, and S. Samanathan, "Branch Effect Reduction Techniques." IEEE Computer, May 1997, pp. 71-81.